-- ejercicio 1 practico 2 utilizando case
-- Implementar un multiplexor de 4 entradas

library IEEE;
use ieee.std_logic_1164.all;

entity pract2 is
port (A, B, C, D: in std_logic;
      SEL: in std_logic_vector (1 downto 0);
	  Y: out std_logic);
end pract2;

architecture ej1 of pract2 is
begin
mux: process (A, B, C, D, SEL)
begin
	case SEL is
	when "00" => y <= A;
	when "01" => y <= B;
	when "10" => y <= C;
	when "11" => y <= D;
	when OTHERS => --;
	end case;
end process mux;
end ej1;